In general, one or more transistor cells (or "chips") are formed on a conductive die, e.g., silicon, which is then attached to a mounting flange as part of a transistor "package." In particular, the conductive die is either attached directly to the flange, or to a non-conductive substrate atop the flange, such as, e.g., beryllium oxide, which acts as an intermediary layer. In either case, a "die-bonding" material, such as, e.g., solder, metal-filled epoxy, or glass, is used to attach the die to the respective flange or substrate. Because the failure rate of transistors is proportional to the temperature of the active area, or junction, of the transistor, one of the most important issues in packaging power transistors is thermal performance. Thus, in order for a die having a plurality of transistors formed thereon to easily transfer heat to an attached heat sink--e.g., via the flange--the die-bonding interface between the die and the heatsink must have a low thermal resistance. Therefore, in addition to providing mechanical support, the bonding material used to attach the die to the package must have a high thermal conductivity.
Epoxy is the most common of these materials and is used in low frequency and DC transistor applications. However, epoxy is a poor thermal conductor, which precludes its use in high frequency applications, such as RF power transistor devices. Instead, hard solders are employed in such devices. Hard solders are relatively low temperature melting alloys that have high strengths, a relatively high thermal conductivity, and are substantially free from thermal fatigue, resulting in elastic, rather than plastic, deformation. Although there exists a number of different hard solders used for attaching dies to packages, a gold-silicon alloy, having a eutectic melting point of 363.degree. C., is the mostly widely used for high frequency applications.
In particular, as illustrated in FIG. 1, the package is heated to 410.degree. C., and the die is then placed on a die attach area of the package (i.e., on the respective mounting flange or non-conductive substrate) with a vacuum tool, and scrubbed against the surface manually until a sufficient melt is formed. A noted problem with this technique, however, is that the die is exposed to relatively high temperatures. In particular, the use of the gold-silicon eutectic as the bonding medium can introduce significant stress in the die upon cooling or under power cycling of the device, due to the lack of plastic deformation ability of the gold-silicon eutectic. These thermal effects can cause cracks if the generated stress exceeds the ultimate strength of silicon. To handle this stress, the use of complex and expensive materials and processes are required. Moreover, to minimize the thermal effects caused by the high processing temperature, the materials surrounding the semiconductor die must have a thermal expansion coefficient that matches that of the die, which greatly limits the choice of materials that can be used.
For instance, referring to FIG. 2, an unsealed prior art power transistor package 10 includes a conductive mounting flange 14 used to conduct heat dissipated from an attached silicon die 12 to a heat sink (not shown). In order to properly perform, the flange 14 must have a thermal expansion coefficient that is approximately that of silicon, (i.e., 2.6.times.10.sup.-6 /.degree.C.). Copper-tungsten (15% Cu), having a thermal expansion coefficient of 7.0.times.10.sup.-6 /.degree.C., is extensively used for this purpose because of its relatively low expansion coefficient. Although this copper-tungsten alloy has a relatively high thermal conductivity (178W/m-K), it would be more desirable to exchange the copper-tungsten (15% Cu) flange with a flange composed of a metal with a higher thermal conductivity, such as pure copper. However, because pure copper has a thermal expansion coefficient (16.5.times.10.sup.-6 /.degree.C.) that is more than six times that of silicon, it cannot be practically used when the chip is processed at the relatively high temperature required for gold-silicon eutectic bonding.
Likewise, even where in intermediary substrate 16 is used to electrically isolate the silicon die 12 from the flange 14, the substrate 16 must have a thermal expansion coefficient close to that of silicon. It must also provide good electrical isolation with minimum capacitance and conductance. Beryllium oxide (BeO), having a thermal expansion coefficient of 8.0.times.10.sup.-6 /.degree.C., is extensively used for this purpose, since it meets the requirements stated above and is fairly inexpensive compared to, for example, industrial diamond, which has the best overall characteristics, exclusive of cost. Nonetheless, the thermal conductivity and expansion limitations imposed due to the die bonding requirement can restrict the use of other, otherwise advantageous substrate materials.
It is, therefore, desirable to provide an alternative process to attach a semiconductor die to the substrate, which can be performed at a relatively low temperature.